This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-402669, filed on Dec. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Background of the Invention
In recent years, the electric power consumed by large-scale integrated circuits (LSI) has risen steadily as the integration density of transistors and the operating frequency has increased. The consumed electric power of a high-end processor already exceeds 100 watts.
In order to suppress the consumed electric power of such LSIs, it is effective to lower the power supply voltage of each transistor.
On the other hand, in order to improve the driving power of a transistor while the power supply voltage is low, a threshold voltage of each transistor must also be lower. However, if the threshold voltage of a transistor is set low, the off current is higher and consumed electric power during the time of waiting is increased.
It is expected that this effect becomes remarkable in situations in which the gate length of a transistor is shorter than 100 nm, that is, in a situation in which a power supply voltage is 1 V and a threshold voltage is no higher than 0.3 V.
One method for solving the problem of electrical power consumption during the waiting period relies on a method in which two kinds of transistors, a transistor having a high threshold voltage and a transistor having a low threshold voltage, are integrated on one LSI chip. In this method, the low threshold voltage transistor, is minute and can operate at high speeds, but has a large off current. The low threshold voltage transistor is used for a principal CMOS logic circuit portion. On the other hand, the high threshold voltage transistor is superior in cut off characteristics and may be used for cutting off a leakage current of a transistor in the CMOS circuit at an off time.
Also, in an LSI with an analog CMOS circuit and a digital CMOS circuit integrated on one chip, it is necessary to integrate transistors having different threshold voltages because the sizes of transistors and power supply voltages in the digital and the analog portions are different from each other.
Transistors having different threshold voltages are conventionally integrated on bulk silicon by changing an impurity concentration of a well. The potential of a substrate is grounded and fixed in the bulk silicon, so that a difference between the work function of a metal used for a gate electrode and the potential of a semiconductor is altered by changing the impurity concentration of the well. As a result, the threshold voltage can be controlled.
In the future, as transistors become smaller and the degree of integration increases, field-effect transistors using an SOI (Silicon On Insulator) substrate, which greatly lowers contact capacitance, will be more commonly used. Among the field-effect transistors using SOI substrates, a complete depletion-mode field-effect transistor is most attractive. This is because a depletion layer reaches a buried insulating film of the SOI substrate at a time of operation that can suppress a short channel effect and perform a transistor operation even if a gate length becomes 100 nm or less.
However, the complete depletion-mode field-effect transistor does have at least one problem. Since a portion of the buried insulating film of the SOI substrate is completely depleted, the body cannot be grounded, and the threshold cannot be controlled by changing the concentration of an impurity. This is because the body is not grounded so that the difference between the work function of a metal used for a gate electrode and the potential of a semiconductor cannot be easily changed even if an impurity is changed. Therefore, the threshold is difficult to control.
As described above, there has been a demand for integration of a plurality of field-effect transistors having different threshold voltages. This integration has traditionally been achieved by controlling the threshold voltages of the field-effect transistors. However, the complete depletion-mode field-effect transistor, which has the advantage of greatly lowering the contact capacitance, has a problem in that integration cannot be achieved by controlling different threshold voltages.
The present invention has been made to solve the above problems, and provides a semiconductor device in which transistors having different threshold voltages can be integrated on one LSI chip, and a method of manufacturing the same.
According to a first aspect of the invention, a semiconductor device comprises: a first lattice-relaxed Si1xe2x88x92xGex film formed on a first region on an insulating film, wherein a Ge composition x is in a range of 0 to 1; a second lattice-relaxed SiGe film having a Ge composition greater than the first lattice-relaxed Si1xe2x88x92xGex film, wherein the second lattice-relaxed SiGe film is formed on a second region on the insulating film; a first strain-Si film formed on the first lattice-relaxed Si1xe2x88x92xGex film; a second strain-Si film formed on the second lattice-relaxed SiGe film; a complete depletion-mode first field-effect transistor including the first strain-Si film as a channel; and a complete depletion-mode second field-effect transistor including the second strain-Si film as a channel, threshold value of the second field-effect transistor is different from threshold value of the first field-effect transistor.
According to a second aspect of the invention, a semiconductor device comprises: a substrate; an insulating film; a first field-effect transistor including a first lattice-relaxed Si1xe2x88x92xGex film having a Ge composition x in a range of 0 to 1 and formed in a first region on the insulating film, a first strain-Si film formed on the first lattice-relaxed Si1xe2x88x92xGex film, a first gate insulating film formed on the first strain-Si film, a first gate electrode formed on the first gate insulating film, and a first source region and a first drain region separately formed in the first strain-Si film; and a second field-effect transistor including a second lattice-relaxed SiGe film formed in a second region on the insulating film, a second strain-Si film formed on the second lattice-relaxed SiGe film, a second gate insulating film formed on the second strain-Si film, a second gate electrode formed on the second gate insulating film, and a second source region and a second drain region separately formed in the second strain-Si film, wherein a threshold voltage of the second field-effect transistor is different from a threshold voltage of the first field-effect transistor.
According to a third aspect of the invention, a method of manufacturing a semiconductor device comprising: forming a first SiGe film and a second SiGe film having different thickness on an insulating film; forming a first lattice-relaxed SiGe film and a second lattice-relaxed SiGe film having different Ge compositions by oxidizing the first SiGe film and the second SiGe film from surfaces; forming a strain-Si film on the first lattice-relaxed SiGe film and the second lattice-relaxed SiGe film; forming a gate insulating film on the strain-Si film; and forming a gate electrode on the gate insulating film.
According to a fourth aspect of the invention, a method of manufacturing a semiconductor device comprising: forming an SiGe film on an insulating film; forming a mask having an opening portion on the SiGe film; oxidizing a top surface of the SiGe film under the opening portion of the mask to form a first lattice-relaxed SiGe film under the mask and a second lattice-relaxed SiGe film under the opening portion of the mask simultaneously, wherein a Ge composition of the first lattice-relaxed SiGe film and a Ge composition of the second lattice-relaxed SiGe film are different; removing the mask; forming a strain-Si film on the first lattice-relaxed SiGe film and the second lattice-relaxed SiGe film; forming a gate insulating film on the strain-Si film; and forming a gate electrode on the gate insulating film.